1. Field of the Invention
This invention relates to the fabrication of integrated circuits and more particularly to such fabrication employing ion implantation for all dopant layers.
2. Description of the Prior Art
Conventional processes of the fabrication of integrated circuits, and more particularly bipolar integrated circuits, employ a number of masking steps to implement the growth of epitaxial oxides and other layers, the etching of those layers and the substrate as well as diffusion of impurities into those layers and so forth. The greater the number of steps that are involved, the greater the time required and the cost of fabrication of such circuits. Furthermore, as the number of masking steps increases, the alignment of such masks requires greater tolerances with the result that the resolution to which the masks can be made is decreased and the dimensions of the devices being formed are increased. This results in a reduction in the packing density of the circuits being formed on the chip. Furthermore, the greater the number of high temperature processes the greater is the growth of crystal defects that limit the yield of good devices.
A particular fabrication technique that allows for a reduction in process and masking steps is the employment of ion implantation. Ion implantation allows for controlled dimensions and more shallow and smaller regions to be created in the semiconductor substrate. The extensive use of ion implantation requires a less number of thermal processing steps for annealing and dopant drive-in as well as a reduction in the use of wet chemicals and toxic gases. It provides for improved device parameter control and the independent control of different device parameters. Although ion implant has been employed in both bipolar and MOS integrated circuits, not all the doping layers of the bipolar device have been created by ion implantation, particularly in the case of the buried collector. This is primarily because of the damage caused to the substrate by the heavy concentration of ions or dopants required to form the collector region.
Another technique that allows for smaller dimensions has been the development of alignment processes whereby different elements of the integrated circuit devices are formed by different portions of the same mask. Examples of self-aligning processes include the Sanera U.S. Pat. No. 3,560,278; the Hunt, et al. U.S. Pat. No. 4,021,270; and the Schwettmann U.S. Pat. No. 3,928,082. The employment of self-alignment for the emitter, base and collector contacts with the same mask, requires fewer etching steps and thus fewer fabrication and handling steps.
Another technique that allows for smaller dimensions has been the development of isolating the individual devices by surrounding them with nonconductive regions. This allows for the devices to be placed closer together without leakage occuring in the substrate between devices and improves performance by reduction of parasitic capacitances. Such techniques include the provision of oxide regions around the individual devices as opposed to the conventional technique of diffusion of dopants which cause a different conductivity so as to achieve junction isolation. Such techniques, particularly the oxide isolation technique, require that the oxide region be gworn through an upper epitaxial region to the silicon substrate, however, such oxide regions are not always buried to a sufficient depth to provide proper isolation without using excessive temperatures or causing undue lack of planarity of the devices surface. Furthermore, in prior art bipolar devices, the buried collector region is formed in the silicon substrate and then an epitaxial silicon layer is grown thereover. The isolation regions are then grown in the epitaxial region. If the isolating regions are not formed to sufficient depth leakage begins to occur between the devices.
It is then an object of the present invention to provide an improved process for the fabrication of integrated circuits.
Is it another object of the present invention to provide an improved process for the fabrication of bipolar devices which require fewer fabrication and handling steps.
It is still another object of the present invention to provide improved process for high performance, high density, high yield potential bipolar circuits.
It is a further object of the present invention to provide an improved bipolar integrated circuit wherein all dopant layers are formed by ion implantation.